1. Technical Field
The present invention generally relates to techniques for reducing electromagnetic interference and in particular to clock spreading.
It finds application in particular, while not exclusively, in Radio Frequency components of Digital Signal Processors (DSP).
2. Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
In Radio Frequency components implementing digital blocks, synchronous logic can generate spurs at every multiple or divisor of a clock frequency. In order to improve digital signatures and to decrease electromagnetic interferences, a technique called clock spreading can be used in order to spread the energy in a large range of frequencies. Electromagnetic interferences can be due to electromagnetic induction or electromagnetic radiation from an external source.
Thus, the goal of such technique is to change the length of the clock period, so that the clock period looks random.
According to systems of the prior art, the frequency of the clock can be varied either by modulating a Phase Locked Loop (PLL), which is an analogical approach, or by changing some clock division ratio, which is a digital approach.
If digital hardware implemented data with uniform distribution is required, Pseudo Random Binary Sequence (PRBS) can be used, which can be implemented with a Linear Feedback Shift Register (LFSR).
Referring to FIG. 1, there is shown a LFSR according to the prior art. The LFSR comprises a plurality of latches 1.1-1.5, which are serially connected, each latch storing a binary value. At each clock cycle, the binary values are shifted, from latch 1.1 to latch 1.2, from latch 1.2 to latch 1.3, from latch 1.3 to latch 1.4 and from latch 1.4 to latch 1.5. The binary value of latch 1.5 is used as output of the LSFR. The binary value of latch 1.4 is transmitted to a logic gate 2 (for example a XOR gate) with the binary value outputted by latch 1.5 in order to inject a new binary value in latch 1.1.
Thus, an N bits LFSR (5 bits on FIG. 1) can generate two sequences:                only 0 when the LFSR is initialized to 0, and        all numbers from 1 to 2n−1 when initialized to anything else.        
LFSR implements a polynomial in Galois field [0:1]n, which coefficient can thus be either 0 or 1. Most Significant Bit (MSB) is 1 and defines the length of the sequence which is 2n−1.
Then, based on the value outputted by latch 1.5 and based on high speed clock, some calculation can decide when the spread clock toggles. The clock signal is then spread depending on the output value of the LFSR.
However, according to the system illustrated on FIG. 1, all LFSR sequences are odd, as their length is equal to 2n−1. The obtained statistics for the value outputted by the LFSR are:                2n−1 times the binary value ‘1’;        2n−1−1 times the binary value ‘0’.        
Thus, the distribution of the binary values is non-centred, resulting in a frequency that is tricky to calculate or to implement. Indeed, such an implementation does not allow to easily determining frequencies to be associated with each binary value, so that an average frequency over a whole period is equal to a target frequency.
In addition, time spreading of the clock should be well known because of some requirements of RF components such as backend constraints or minimum throughput. This is not enabled by the systems of the prior art, for which minimum frequency is hard to predict and is very low on existing implementations.
Thus, there is a need to improve the accuracy and efficiency associated with clock spreading.